Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter

FPGA-based digital IC testers have been commercialized and shown to be a promising solution for low to mid-end applications. For FPGA-based test equipment to be a practical solution, it is crucial to increase the number of channels that one single FPGA can accommodate. The objective of this work is to develop a data/timing formatter architecture that consumes less FPGA resources so as to accommodate 16 formatter channels in one Xilinx Spartan 6 FPGA. To reach this goal, the proposed formatter utilizes the more compact time/format set tables to store the pre-processed control signals and delay codes required for symbol generation. To match the time/format set table based symbol generation, a new EG (edge generator) pool structure is developed; it also lowers FPGA resource usage without sacrificing the timing accuracy. Furthermore, the EG is redesigned to reduce the controller timing complexity. The proposed 16-channel formatter has been implemented on a Xilinx Spartan 6 FPGA. Compared to the previously reported 5-channel formatter, it delivers the same performance (200 ps edge placement resolution and 100 MSPS symbol rate) without significant increase in FPGA resource usage.