A Methodology to Emulate the Effect of EMI in Circuit Simulators for Wireline Communication Channel

This letter presents a methodology to model the effect of electromagnetic interference (EMI) on the wireline communication channels. The proposed simulation methodology incorporates the effect of EMI on the circuit during the design phase in EMI-sensitive applications. It allows simple and faster EMI simulations at the SPICE level which minimizes the post-fabrication failures. A TEM (transverse electromagnetic) cell is used to emulate the effect of EMI on the test circuit as provided in the standard IEC-62132. An analytical model is presented to quantify the effect of induced voltage and current on a transmission line placed in the TEM cell. The developed model is experimentally verified for a frequency range of 1 MHz to 1 GHz. As an experimental study, the proposed model is used to validate the effect of EMI on the wireline communication channel transmitting a pseudorandom binary sequence (PRBS) data generated from an FPGA board at 1 Gbps data rate for a wide range of EMI powers and frequencies.

I. Introduction

With the continuous miniaturisation of electronic circuits, a large number of electronic components are integrated within a small board space. This intensifies problems such as cross-talk and interference. Furthermore, the exponential adoption of electronic equipment pollute the environment with electromagnetic (EM) radiations. These EM radiations are received by the electronic systems as an undesired electromagnetic interference (EMI) and disturb the desired operation of the circuit. Many cases of circuit failures, which have been caused due to EMI, have been explored by researchers [1]. As a result, throughout the electronics community, regulations have been enforced to make instruments electromagnetic compatible [1]. The standard IEC-62132 indicates the measurement methodology to test the electromagnetic immunity (EMI) of IC to radiated and conducted interference. A detailed explanation of test conditions, setup and equipment to test the EMI immunity of any circuit is given in IEC 62132 [2].

Take-Home Messages: •

RMI-immunity of the circuit must be considered during the design phase to prevent post-fabrication failures.

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A simple model is proposed in the paper enabling co-simulation of the KM I effect during circuit operations without adding extra timely simulations.

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Mathematical equations are derived for the induced voltage and the current required for the proposed model.

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The accuracy of the proposed model is experimentally verified using an off-chip interconnect carrying PRBS data in an EMI environment as a test circuit.