A Digital Self-Calibration Technique for 16-bit SARADC

In this paper, a new digital calibration algorithm is proposed to reduce the circuit area by means of reusing the digital circuit while ensuring the accuracy of the calibration capacitor array. The algorithm is applied to a 16-bit 200KS/s 4 channels sar adc, fabricated in EMC 55-nm process. The simulation result shows that the ENOB of the SAR ADC is raised from 10.85 bits to 15.25 bits, and the SNDR is from 67.07dB increased to 93.54dB. SFDR increased from 70.66dB to 110.6dB. DNL remained at
${\pm 0.8\mathrm{LSB}}$
, and INL remained at
${\pm 1\mathrm{LSB}}$
after the calibration algorithm is adopted.