A 10-bit Dual-Channel Current Steering DAC in 40nm technology

This paper describes the design of a 10-bit dual-channel 32 MS/s segmented current steering digital-to-analog converter (DAC) for communication applications. The DAC is segmented as 6+4, where the 6 MSB bits are implemented in unary and 4 LSB bits are realized in binary architecture. It is implemented in TSMC 40 nm CMOS technology. The supply voltages are 1.1V. The layout is occupied 0.15 mm
²
and the measured spurious-free dynamic range (SFDR) is 71.35 dBc with a input sinusoidal signal of 10MHz.