A Study of LDE on Stdcell Device Performance in Advance FinFET Technology

In this paper, a novel method is demonstrated to provide quantitative analysis of layout dependent effects (LDE) on Standard cell (Stdcell) devices. The impact of each LDE was split by model simulation and correlated with silicon statistics of over 3000 Stdcell devices, indicating an accurate relationship between device performance, S2S (silicon to simulation) gap and LDE-induced shift. It is also exhibited that LDE shows more impact on PMOS variation than it does on NMOS variation. This work provides a useful guideline for designers to filter risky Stdcell devices in the early stage of advanced FinFET technology.