A 38 ∼ 40.5 GHz Frequency Divider Chain for FMCW PLL

This paper mainly realizes a 38 ~ 40.5 GHz frequency divider chain in TSMC 65 nm. The divide ratio is 760 ~ 810. The total divider chain consists of 3-stage dividers: ILFD, CML and pulse swallow divider. The ILFD is equipped with alternative DC bias. The pulse swallow divider includes 8/9 dual modulus prescaler, digital counters and ΣΔ quantizer. Dual modulus prescaler consists of 5-stage TSPC D flip-flops in newly high-speed structure. The input range can achieve 34 ~ 43 GHz at tt 25 °C. The phase noise is -143.5 dBc/Hz at 100 kHz and -152.2 dBc/Hz at 1 MHz. Total power consumption is 23.27 mW and area of analog part is 180 um × 275 um. In 0 ~ 60°C and fully corners, the input range achieves 37.5 ~ 41 GHz.