Investigation of DIBL Degradation in Nanoscale FinFETs under Various Hot Carrier Stresses

In this paper, the degradation of drain-induced barrier lowering (DIBL) in FinFETs is experimentally studied under various hot carrier degradation (HCD) stress conditions. A test method is developed to characterize channel barrier height modulation under different HCD stress conditions. A linear relationship of ΔV
_thlin
and ΔV
_thsat
after HCD is found. Then a compact model of HCD-induced ΔDIBL is proposed. The results are helpful for the physical understanding and modeling of HCD in nanoscale FinFETs and aging-aware circuit design.