Recent Advance on Floating Random Walk Based Capacitance Solver for VLSI Circuit Design

Capacitance extraction for interconnect parasitics modeling is the basis of accurate circuit simulation and physical verification for quality integrated circuit (IC) design. Due to its scalability and reliability, the floating random walk (FRW) based solver has been widely used for the capacitance extraction. In this paper, the recently developed techniques on distributed parallel FRW solver and for handling complex floating metals are presented. With them, the efficiency and accuracy of capacitance extraction/simulation for very large-scale integration (VLSI) circuit design are remarkably improved.