An ADC Input Buffer with Optimized Linearity

In order to achieve high performance of analog-to-digital converter (ADC), a high-linearity input buffer is needed, especially for IF/RF sampling applications. In this paper, a wide-band input buffer with optimized linearity is proposed. Techniques of AC floating n-well and negative bulk biasing are used to suppress and linearize the parasitic capacitance in the output of the input buffer, hence improve the total linearity. The post simulation results show that the proposed input buffer achieves significant SFDR improvement across a wide input frequency range compared to the conventional circuit. The input buffer operates from a 2.5V supply and consumes 30mA, with input full scale of 1.8 V
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