A Linearity Enhancement Technique for Cascode Opamp in 65nm CMOS Technology

In this paper linearity of standard opamp and importance of this parameter for typical applications like continuous-time filters have been discussed. Out of few factors affecting the linearity, drain to source voltage of the differential pair has been root caused to this problem. A technique to improve the linearity by using a common mode feedback applied to the Cascode devices was proposed. A test circuit developed in 65nm CMOS technology to verify the robustness of the proposed technique and post-layout simulations shows 45% linearity improvement compared to the conventional architecture. Circuit operates at 1.2V and draws 235μA static current and test circuit occupies 4500um
²
silicon area.