Low Power Dynamic Comparator Design for High Speed ADC Application

Comparator is the heart of Analog to Digital Converter (ADC). In order to design a ultra less power consuming, small delay ADC it force us to design a dynamic comparator to maximize power efficiency and speed. The main use of comparator in ADC be comparison of a given input continuous analog signal along with certain threshold signal to give a output signal depend on whether the analog signal is higher or lower than the threshold signal. Here paper designs a pre-amplifier based comparator utilizing cadence tool. In this proposed design the MOS transistor of length 180nm and width of 720nm and the power supply in the range 1.2V to 1.8V were used. Here the proposed deign has been implemented in various CMOS families using cadence virtuoso 180nm CMOS technology its performance has been simulated and compared to choose the best among them based on power consumption and delay. From the comparison table, it is concluded that the proposed dynamic circuit that is un footed consumes the least power of 51.3μW with the delay of 208pS.