UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol

The scale and complexity of integrated circuit designs are ever expanding which makes the verification process increasingly difficult and progressively time consuming. This dictates the need for testbench architectures with generic verification components that are reusable and easily extendable across designs. The UVM can realize such testbench architectures with coverage driven verification environments useful for constrained random testing. This paper focus on the UVM based verification of SPI protocol according to the verification plan prepared after an exhaustive analysis of SPI functional specifications. The UVM testbench generates random vectors, drives the SPI module and compares the captured response with expected response using scoreboard mechanism to verify the SPI functionality. The testbench also validates the characteristic features of SPI by running appropriate test cases and reports coverage cumulatively at the end of each test. The simulation results are analyzed to evaluate the effectiveness of the proposed testbench.