A Parallel Pipelined Adder Suitable for FPGA Implementation

A smart city should indispensably use Internet of Things wherein various things are embedded with electronics to facilitate exchange of information. This exchange of information requires the things to be perpetually connected to each other with zero down time. Owing to the parallel pipelined capability of a Field Programmable Gate Array (FPGA) coupled with its low power consumption, FPGA can prove to be an ideal candidate for the connections. This paper proposes the design of a parallel pipelined adder in an FPGA which is the basic arithmetic block required in any device for basic processing tasks.