Development of a wafer level packaging technology for high voltage applications

TSV first or TSV last are technologies used in 3D packaging, that are now well described in the literature. However there is still room for some improvement especially in the field of TSV isolation. Certain applications such as power applications or light emitting diodes serially powered on the 230 Volts-50 Hz network require some trench isolation for wafer level packaging. In this case the breakdown voltage (up to 600 V) of the trench/TSV becomes a critical issue. In this study different organic and mineral passivation layers were tested to classify their resistance to high voltage. The impact of the Temperature process and the deposition method is shown. Some thermal oxides are also tested and the breakdown voltage is found to be around 800V/μm. Some FEM simulations were achieved showing the influence of the trench geometry. The oxide is then implemented on pixelated samples fabricated on 200mm highly doped Si wafers. Experimental measurements show a breakdown voltage location at the trench crossing zone and a value of 400μm/V in accordance with the FEM simulations.