Towards Reconfigurable HPC Component Models

High performance computing (HPC), as other domains, is facing growth of the complexity of both hardware and software. Hardware complexity can be observed in the diversification of computing units (multi-core, many-core, GPGPU, FPGA, etc.) and, more recently, in storage elements (SSD and then SVRAM). Many of these new technologies stem from frequency scaling limitations and energy consumption issues. Hence, not only do applications have to be continuously adapted to varied and changing hardware configurations, but also energy-related concerns encourage runtime adaptation to use as little resources as possible.