Design of High-Speed and Energy-Efficient Parallel Prefix Kogge Stone Adder

In the recent decades, the demand of mobile electronic devices is exponentially increased which creates a urge to design highly effective VLSI structures. The operations in the devices necessitate to be computed by low-power, area-efficient designs which operates at higher speed. Addition is the commonly used arithmetic operation; and adder is the basic arithmetic element of the processor. Presently, Carry Skip adder (CSKA) is found to be an effective adder which is compact and consumes less power. But, the lower speed of CSKA became a major drawback and it fails to employ in high-speed applications. To overcome the limitations of CSKA, a faster and efficient Parallel Prefix Adder (PPA) is introduced, which is developed from the carry look ahead adders. In this paper, we design and develop a new PPA architecture namely Kogge Stone adder (KSA) for 8, 16, 32 and 64-bit addition. The proposed method is implemented and the results are compared with CSKA interms of area, delay, speed and power consumption. Simulations results on Kogge Stone adders (KSA) reveal minimization of power consumption compared with the CSKA along with area compaction and high speed.