Pico-TDC: a novel FPGA-based TDC with 2.2ps RMS timing resolution

The purpose of this work is to develop low-cost highperformance TDCs to meet the requirement from the next generation sub-10ps TOF-PET camera. A TOF-PET system may need hundreds of high resolution TDCs to read timing from many detectors. FPGA-based TDC designs, such as conventional delay-line (DL) TDCs and Wave-Unions (WU) TDCs, are a more viable solutions compared with expensive ASIC-based TDCs. However, the performances of those FPGA-based TDCs are more or less depended on the specific structures and performances of the delay lines, which are usually the carry chains in the adders of a FPGA. In this paper, we present a new method called Pico-TDC method to construct the TDCs in FPGA. The uniqueness of the Pico-TDC method is to use single registers in the FPGA as lowprecision TDCs, and to combine many of those low-precision TDCs to construct a high-precision TDC. The advantages of PicoTDC method are: (1) the timing performance of a Pico-TDC is not limited by the performance of delay lines in the FPGA. As a result, it is possible to achieve unprecedented resolution with a {low-cost FPGA. (2) Hundreds of high-performance Pico-TDCs can be constructed in a low-cost FPGA which normally has millions of registers. (3) Theoretically, the Pico-TDCs can be conveniently migrated from one FPGA to another, regardless of the differences in the internal structures of the FPGAs. We have successfully constructed four channels of Pico-TDCs in a low-cost FPGA (Altera Cyclone V 5CEBA4F23C7N, price: $66.63). Each TDC uses 640 registers (low-precision TDCs). The four Pico-TDCs were tested with both the internal and the external pulses. The RMS of the timing measurements is 2.2 ps. The temperature stability is excellent. We conclude that PicoTDCs have excellent timing performance which meets the requirement of the next generation sub-10ps TOF-PET.