A Bayesian Framework for Optimizing Interconnects in High-Speed Channels

Increasing demand in higher bandwidth chip-to chip communications have resulted in challenges related to modelling and optimization of their electrical performance due to CPU intensive simulations arising from multiscale structures. Conventional approaches use various approximations to either reduce the design complexity or reduce the simulation time, however, this can lead to inaccurate models and sub-optimal designs. In this paper, we address this problem by using machine learning based techniques and propose a Bayesian framework to model and optimize interconnects in high-speed channels in an accurate yet efficient fashion.