A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS

This paper presents a digital bang-bang phase-locked loop that employs background injection timing calibration and automatic loop gain control to enhance the jitter and spur performance against PVT variations. The chip is fabricated in 7nm FinFET technology. This bang-bang phase-locked loop achieves 426.5fs
_rms
integrated jitter and -61dBc reference spurs, occupying an area of 0.018mm
²
(120μm×150μm). The FOM is -239.4dB at 4GHz output frequency.