An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS

An open-source out-of-order superscalar processor implements the 64-bit RISC-V instruction set architecture (ISA) and achieves 3.77 CoreMark/MHz. The 2.7 mm×1.8 mm chip includes one core operating at 1.0 GHz at nominal 0.9 V with 1 MB of level-2 (L2) cache in a 28 nm HPM process. A line recycling (LR) technique reuses faulty cache lines that fail at low voltages to correct errors with only 0.77% L2 area overhead. LR reduces minimum operating voltage to 0.47 V, improving energy efficiency by 43% with negligible impact on CPI.