A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR

This paper presents a two-step incremental ADC (IADC) with extended counting. The proposed IADC has only one active integrator in the two-step conversion cycle. To achieve high accuracy without trimming or calibration, a cyclic ADC with a 31-level quantizer is used in the second step. Fabricated in 0.18 μm CMOS process, the prototype ADC occupies 0.72 mm². With a 55 MHz clock, the measured dynamic range and SFDR are 100 dB and 110 dB, respectively, at a conversion rate of 1.25 MS/s. The power consumption is 27.7 mW from a 3 V power supply. This gives a Schreier FoM of 173.6 dB.

Introduction

For ADCs in the field of industrial robots, low latency, high dynamic range (DR) (> 90 dB) and wide bandwidth (> 0.5 MHz) are required for the feedback control. However, it is difficult to realize high DR by using SAR ADCs due to the capacitor mismatch. Although incremental ADCs (IADCs) have inherently high linearity, the requirement of a high oversampling ratio to obtain a high resolution limits the bandwidth in a first order modulator. A higher order modulator was proposed [1], but this architecture suffered from potential instability and from more power consumption. To solve these problems, multi-step IADCs with extended counting were proposed [2]–[4]. However by using a SAR ADC as extended counting [2], the size of the CDAC increased and the second order modulator was required for high DR to reduce the effect of the capacitor mismatch. By using a cyclic ADC [3], the required multiplications by a factor of 2 limited the achievable accuracy. A multi-slope scheme in [4] realized high DR of 99.7 dB, but it required many conversion cycles.