Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

Exceptionally low minimum operating voltage (V
_MIN
) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm
²
high-density bitcell (HDC) and 32Mb array of 0.107μm
²
high-current bitcell (HCC) achieve the 95
^th
percentile V
_MIN
of 505mV and 450mV respectively across a temperature range of -10°C to 95°C. A self-induced collapse (SIC) write assist integrated into the 6-T HDC SRAM bitcell array enables 110mV V
_MIN
reduction relative to an unassisted array at the 95
^th
percentile with negligible power overhead.