Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver

This paper presents a new scheme of clock synchronous reset and a two-step clock skew calibration method in multi-lane time-interleaved ADC based coherent receivers. The synchronous reset scheme eliminates metastability in clock generation circuits and guarantees reliable synchronization of sampling and de-serializing among all lanes. The skew calibration compensates for both inter-lane and intra-lane timing mismatches in critical quadrature sampling clocks. Our proposal is demonstrated in a fully integrated coherent receiver including 4 lanes of 65GS/s 8-bit ADC fabricated in 16nm FinFET CMOS.