Analysis of Different Magnitude Comparator Using Subtraction Logic

In this paper we have designed one, two and four bit comparator. In the proposed circuitry we have discussed different way of designing the circuit and analyzing the power, area, delay and transistor count of various circuits. In this paper we have discussed the novel architecture of a comparator using subtraction logic which has more improved parameter comparing with others. We have designed a 6T XOR gate which makes the transistor countless from 12T to 6T. Designing of all the circuit is done on cadence virtuoso 180 nm technology with a supply voltage of 1.8v.