Digital design and implementation of an overcurrent relay on FPGA

Protection relays are an important component of a power system, which are used to minimize the disturbances caused by the internal and external faults of the system to ensure the continuous power supply. Overcurrent relay (OCR) is the most economical and widely used component in the power system protection. The OCR operates by tripping the circuit breaker when the fault current increases above the threshold value. This paper presents the design and implementation of an inverse definite minimum time (IDMT) OCR on the reconfigurable hardware i.e. field programmable gate array (FPGA). Two types of inverse characteristics (i.e. Very and Extremely inverse) are considered in the paper. An efficient moving window, root mean square estimation module is proposed in this design which reduces the hardware requirement of the chip. Finally, the accuracy of the design is verified for different values of peak-up current and time dial settings. The relay is implemented on Xilinx Virtex ML-505 FPGA Board. The proposed relay meet the characteristics of the IEEE standard C37.112-1996 for overcurrent relays.