Analysis of Power Reduction Techniques in Digital Circuits in Submicron Regime

With continuous scaling of technology, density of transistor is increasing which leads to higher power dissipation on the chip. Therefore the need of the hour is to reduce the power consumption of individual circuits. In this paper a new mixed logic of TGL and DVL a power efficient circuit is proposed. The proposed adder is operated at 0.9V supply with 1.894 μW in 90 nm NG-spice CMOS process technology.