High Performance Network on Chip using AXI4 protocol interface on an FPGA

In todays FPGA platform the On-chip Network communication has become an important significance. Mainly the real-time applications have a good prominence in the embedded field. The main intention of study in this paper is to understand the communication in NOC using the advanced version of AMBA AXI protocol. This paper discusses the challenges faced and experimental analysis in the design of on-chip communication using AXI4 Protocol. This protocol version we are using here as it is the advanced version which helps in simple interface registering for all the applications with multiple masters. Network on chip determines a system of communication on-chip basically an integrated circuit i.e. IC. This is practiced rapidly in all aspects at industry level because it offers the advantage factors like scalability in the system on chips compared to SOC and power efficiency levels. The main key challenge of this paper is to provide an architecture with efficient Quality of service, good transmission rate, less complexity in routing interfaces and bandwidth challenges for all burst lengths in data transmissions.