Implementation of Area and Power Efficient Components of a MAC Unit for DSP Processors

In today's era power, delay and area have become the characteristic features of any VLSI circuit. Generally, the delay of ordinary multipliers is more and so is the amount of calculations, as a result of this the overall speed of circuits gets reduced and the power consumption is high. In this paper the two major components of MAC unit i.e. i) Multiplier (8×8 Vedic Multiplier and 8×8 Booth Multiplier) ii) Adder (Carrylook ahead adder) have been designed. A comparative analysis is done between these two multipliers in terms of power and area. Power analysis of the two multipliers is done with Xpower Analyzer tool which shows a power consumption of 0.249 W for Vedic multiplier and 0.267W for Booth multiplier. Area analysis is done by comparing the availability and utilization of the resources used while designing the multipliers. It has been found out that Vedic multiplier is more efficient than Booth multiplier in terms of both, power and area. To implement this design VHDL language has been used as Hardware Description language and simulated on Xilinx Vivado 15.4 Software tool.