Design of a LP Current-mode Comparator Based on Positive-Feedback Source Coupled Logic

This paper presents a clocked current comparator based on Source Coupled Logic (SCL) style and its variant called Positive Feedback Source Coupled Logic (PFSCL). The operation of the proposed comparator is verified through simulations using 90nm CMOS technology parameters. The maximum clock frequency of the proposed comparator can be increased to 100 MHz while consuming 23uW of power with 5ns delay time.