Low-power Time-to-Digital Converter Based on Vernier Gated-Ring-Oscillator

This paper introduces a time-to-digital converter (TDC) based on Vernier gated ring oscillator (GRO) with high resolution and very low power consumption for biomedical imaging applications. The effective blocks in the power consumption of this converter include two ring oscillators, a single-transition end-of-conversion detection array block, and finally an Arbiter array block. This paper has greatly improved the power by modifying the Arbiter block structure. This converter has been simulated in the
$0.18\mu \mathbf{m}$
CMOS technology with a supply voltage of 1.8 V. The proposed 8-bit Vernier GRO has a resolution of 14.3 ps. By using a dynamic D-type flip-flop for implementing the arbiter block and applying a few modification to ring-oscillators control circuit, the power consumption is reduced by 65% compared to the original design. The Monte Carlo analysis in 400 runs, including both process and mismatch variations, shows the standard deviation of 3-code in the output code for the proposed structure.