Process Development and Failure Analysis for Chip-Last Panel Level Fan-out Packaging (PLP)

Nowadays, fan-out package is regarded as one of the most potential packaging technologies because of its thinner profile, lower cost, better thermal and electrical performance. However, there are still challenges for manufacturing process including precise alignment of die bonding and large warpage of the molded wafer/panel, etc. In this study, a novel 320mm×320mm panel level fan-out package based on die last process is developed. The challenges of this process technology, such as die jumping, die shift, delamination and warpage are studied, corresponding failure analysis was conducted accordingly. It is found that large warpage of the substrate and voids or bubbles (without proper taping by using vacuum methods) during reflow process are the main issues and may induce delamination of the substrate and FR4 carrier, and cause die jumping and non-wetting of solders. And die shift is also found to be a critical issue due to the limitation of die attachment precision. Therefore, reducing warpage of substrate, minimizing the trapped voids and bubbles and improving die bond accuracy are major solutions for achieving high yield and high quality of chip last processing during panel level packaging (PLP).