Thermal Stress Analysis and Design Guidelines for Through Silicon Via Structure in 3D IC Integration

Through Silicon Via (TSV) technology has been a preferred and promising strategy to achieve the reliable interconnection for the integration of 3D IC. The temperature made some changes within the procedures of the manufacture of TSV and the adoption of chips because of the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials adopted within TSV structure, important thermal stress is going to be induced under the thermal load. The stresses are possible to cause different reliability problems. Dimension parameters are going to influence TSV's thermal behaviors. For the purpose of optimizing the design of TSV, Cu-filled TSV's numerical model had been set up for simulating and analyzing the influence of the thickness of SiO
₂
, aspect ratio (AR), diameter and shape upon TSV thermal stress within the paper. The outcomes of the simulation present that the maximum of the areas of equivalent stress always happens at the bottom and top of the interface of Cu/SiO
₂
. The aspect ratio's influence on the equivalent stress is rather small when aspect ratio is more than 6 for vertical TSV. Vertical TSV with thicker SiO
₂
layer may improve its reliability. However, the SiO
₂
layer thickness does not have obvious influence for the inclined TSV upon equivalent stress.