Modeling the Hysteresis Power Losses of the Output Parasitic Capacitance in Super Junction MOSFETs

High switching frequencies in power converters allow to use small-size passive components that, in turn, means high-density (kW/kg) power conversion. The use of silicon MOSFETs manufactured with super junction technology is an additional feature towards the achievement of very high-density converters. The concurrent factors of increased switching frequency and power density may lead to thermal issues to be faced. Aiming to reduce the overall power losses, soft switching techniques are adopted to reduce dramatically the switching power losses, thus increasing the efficiency. The application of super junction (SJ) MOSFETs in soft-switching based conversion schemes has revealed unexpected power losses due to the dielectric hysteresis phenomenon into the parasitic output capacitance Coss of the MOSFET. In this respect, the experimental evidence has proved that there is a very large performance difference among the devices available into the market. This paper studies the Coss power losses that have been experimentally measured, modeled and simulated by a PSpice package. The proposed model is a nonlinear resistor whose average value is equal to the equivalent series resistance calculated from the experimental hysteresis loop (Q- V characteristic) and the related power losses at a given switching frequency.