Measurements of Critical Charge Around Rising Edge of Clock Signal

This paper analyzed the critical charges of a master-slave D-FF when a soft error occurred around a rising edge of a clock signal. We measured the critical charge around a rising edge of clock signal, and then compared that when CLK is stable. This analysis showed that single events can bring about an upset even when the master latch is in a transparent state (i.e. CLK = 0) around rising edge of clock signal while event do not incur an upset when the master latch is stably in a transparent state. Furthermore for CLK=0 there is a period in which the critical charge is lower than that for CLK=l. In our simulation., the period occurred 0.1ns prior to the clock edge.