Design of Two LNA Topologies in 0.35 µm CMOS Technology for 2 GHz Frequency Range

This paper presents two LNA topologies for 2 GHz frequency range. The aim was to investigate the impact of inductors on the design flow of the amplifiers. The first topology contains two inductors and utilizes two feedback paths (positive and negative), while the other topology is inductorless and has two signal paths splitting up the input signal and adding them back together after amplification. The LNAs achieve gains of 15.8 dB and 14 dB respectively, and noise figure (NF) of 6.5 dB-7.2 dB. The IIP3 post-layout simulation results show -2.83 dBm and -1.82 dBm, the DC power consumption is 27.2 mW and 22.36 mW at 3.3 V supply voltage, respectively. Both topologies are stable over the frequency range of interest. The LNAs are designed with AMS 0.35-μm CMOS process. Designs occupy total area of 0.171 mm
²
and 0.029 mm
²
respectively.