Proof of General Switched-Capacitor DC-DC Converter Law using Voltage-Domain Analysis

This work presents a general law of switched-capacitor (SC) DC-DC converter topologies which is derived using a time-averaged voltage-domain analysis. Unlike previous formulations of constraints on a SC converter's basic properties, the presented law describes for the first time a fundamental relationship in equality between a topology's VCR and its capacitors' bias voltages, bottom-plate voltage swings and charge multiplier vector simultaneously. Using this law, a definition for topologically efficient topologies is identified. Furthermore, the proposed voltage-domain analysis can also be used for visual topology synthesis.