Analog Power Filtering: Modeling, Measuring & Analog PI

This paper discusses a methodology for developing, measuring and optimizing analog power isolation for general computing applications. The authors present mathematical filter circuit derivation, a modeling and simulation technique as well a measurement verification approach applicable to analog power domains. The filter applications considered within this study include high-current domains for powering digital logic as well as those for powering noise-sensitive on-die circuits within processor and custom ASIC applications. The noise sensitive analog circuits include PLLs, SERDES and clock circuits. While peak current demand for such analog supplies may be insignificant compared to their digital domain counterparts, the authors discuss ever-decreasing AC noise budgets within the context of increasing processing and IO complexity and density. An effect of realizing said density is that isolating contextually low-current analog power from its digital parent becomes more challenging and critical to the success of the design. This paper discusses that critical role, necessary in the development of successful power distribution networks.