De-sensitization Design and Analysis for Highly Integrated RFSoC and DRAM Stacked-Die Design

For 3G market, the demand drives continuously on highly-integrated, low-cost radios solution. Beyond the development of RFSoC, DRAM SiP is an attractive solution to the entry-level market. Integrating LPDDR3-1066 Mbps die by stacking with cellular and connectivity radios SoC die, the world's 1st 3G RFSoC with DRAM SiP solution was presented in this paper using low-cost and low-profile 2-layer wire-bond TFBGA package. In this design, RDL routing is used for interconnects between RFSoC and DRAM, as well as interconnects for fan-out of all peripheral I/Os. Therefore, the interference from DRAM and RDL routing to RF is the bottleneck of system integration. In order to characterize DRAM noise, an inductor probe was designed to measure the noise level from DRAM and its RDL. Based on the measured data, the stacking placement of RFSoC and DRAM can be determined preliminarily. Furthermore, a test vehicle was developed to verify the DRAM noise effect on RF PLL because its LC tank VCO is sensitive to the interference. From the experiment, a tone near VCO frequency with measured DRAM noise magnitude level is injected into DRAM and then causes spur occurred on LO and results in RF performance degradation, e.g. RX desensitization, TX spectrum mask failure and EVM degradation, etc. In this paper, a simplified equivalent model was proposed to estimate aforementioned coupling effect and performed good correlation between simulation and measurement. Besides, chip-package-PCB co-design flow was also applied to deal with the interference and de-sensitization problem in RFSoC design and this generalized methodology can widely be applied to all kinds of system-on-chip (SoC) / system-in-package (SiP) designs for cellular and connectivity applications.