Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models

Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

I. Introduction

Device variability has become a serious concern for analog and digital circuit designers. Time-dependent variability (TDV) effects like Hot Carrier Injection (HCI) [1] and Bias Temperature Instability (BTI) [2] in NMOS (PBTI) and PMOS (NBTI) transistors add up to the omnipresent time-zero process variations. TDV phenomena have been included in some commercial reliability circuit simulators, e.g., [3]; most of them rely on deterministic models. However, the stochastic behavior of TDV phenomena requires that deterministic models are replaced by stochastic models. Recently, the Probabilistic Defect Occupancy (PDO) model, which considers the stochastic HCI and BTI effects and estimates the transistor degradation as the sum of a permanent and a recovery component, has been developed [4]. Obviously, the models have to be completed with the characterization of aging phenomena at the device level. To that end, device arrays have been frequently used [5].