Soft Error Rate from Planar to FinFETs On Bulk Vs SOI Processes

The Semiconductor scaling from planar to recent 3D Vertical FinFET process, have seen better than expected robustness against soft errors, in addition to significant performance and area scaling. This paper presents the SER scaling trends and comparison between earlier planar sub-micron nodes and FinFETs processes. The SER trends between Bulk Vs SOI processes on FinFET processes are also discussed using SRAM and Logic SER data collected using respective vehicles for comparisons. Also an analytical attempt made to validate if the earlier observed SOI Vs Bulk improvements seen on SER in Planar nodes and the scaling between them is still valid on FinFET processes.