A 1GSps RF sampling pipelined ADC with novel background digital calibration

This paper presents a novel high accuracy background calibration design for pipelined ADC. Pseudorandom (PN) sequences are used for gain error calibration but also limit the calibration accuracy because of the inherent quantization noise. So we add redundant stages and derive new algorithm to reduce the impact of quantization noise and improve the accuracy of gain error calibration. A 12-Bit 1Gsps RF sampling pipelined ADC using our proposed digital calibration has been designed. Both behavioral and post simulation indicates the proposed calibration works effectively, where the post simulation results show the ADC reaches an SNDR of 66.6 dB (ENOB=9.72-Bit) at 1GSps sampling rate after the calibration.