I. Introduction
Cryptographic circuits leak their internal processing and activities through power consumption, electromagnetic emanations and other side-channel information [1]. The power consumption in cryptographic systems is directly related to the input data string and the data being processed. Data dependency correlates the hamming distance of input data and reference data with real power consumption [2], the neglecting of short circuit power leads to equality of switching power consumption with dynamic power [3]. Since dynamic power is the function of power supply voltage, clock frequency and effective capacitance of the circuit nodes denoted by , it can be exploited easily by attackers to reveal the secret key of the cryptographic circuits. In Differential Power Analysis attack (DPA) or Correlation Power Analysis attack (CPA), an attacker can input plaintext and measure the power consumption of cryptographic circuits in specific time intervals and using distinguishers such as Pearson correlation coefficient to detect secret key [1]–[2] [4]. The switching activity of cryptographic circuits leaks information through dynamic power consumption. It includes real and spurious switching; a few literatures have considered or mentioned the impact of glitch from the security perspective [5]–[9]. The power consumption of spurious transitions includes twenty to seventy percent of total dynamic power consumption [9]–[10]. The source of glitch is the signals with different arrival times. In a pipeline cryptographic circuits the primary inputs are synchronized with clock frequency to appear simultaneously at combinational blocks. Whereas combinational blocks consist of different gates with different path delays, it causes some transitions of the circuit nodes to be spurious. This paper proposes a glitch power model to study the implication of glitch power consumption on the security of cryptographic circuits. The rest of the paper is organized as follows. Section II gives the related background works about density transitions and signal probability. Section III investigates the mechanism of glitch generation to make a glitch model from previous literature and proposes a technique to decrease the glitch rate. In section IV the paper will be concluded.