A novel high performance medium-voltage DEnMOS in 40nm CMOS technology

A new kind of symmetric medium-voltage DEnMOS embedded in 40nm CMOS process is developed out for parasitic capacitance improvement and specified on resistance decrease by adding one to two masks except for baseline set. Hot carrier induced degradation and DC measurement result are studied. Our results clearly show that the new concept gets tremendous improvement in both on-resistance and parasitic capacitance.