UVM based testbench architecture for logic sub-system verification

Functional verification is one among t he main bottle-neck in design of complex system designs and it consumes almost 70% of the project cycle. In present scenario, verification using directed testing is a tedious task and time consuming. Also, there will be many uncovered scenarios left out. It will be of advantage if the test bench is reusable, robust, and scalable in SoC verification. Universal Verification Methodology (UVM) along with System Verilog helps in building a coverage driven constraint random verification environment f or verification. This paper analyzes the use of UVM in creating test bench by taking synchronous FIFO as a subsystem under verification. FIFOs are an integral part in almost all SoCs. They are widely used as buffers, queue, flow control etc. in data applications. The Design Under Verification is tested and coverage models are implemented to verify DUV.