A low power high efficiency BPSK transceiver using level converter for communication applications

Transreceivers designed using single supply threshold voltage consists of transmitter section and receiver section where the sub systems of the design use same supply voltage whereas some sub systems may not require the same power requirements for the design. Instead the paper focuses on designing a multi vth level Converter based Transreceiver where a Level converter converts Low to High or High to Low Voltage to different sub systems of the design. In this paper, design of a Dual-Vdd and multi threshold Level converter based Transreceiver using Single Clocking methodology is analyzed with respect its operation then building and testing using Cadence Tools. In realization, first discuss the architecture and the implementation issues. Then, the coding process is simulated and verified by Cadence Tools.