Digital demodulation of the signals phase-shift keyed in toto and coded by walsh sequences

We consider the possible characteristics of the digital demodulator of the signals phase-shift keyed in toto and coded by Walsh sequences and the ways of hardware implementation of such a demodulator by means of programmable logic devices (PLDs). We introduce the fast digital algorithm for noncoherent demodulation of the phase-shift keyed signals coded in toto, requiring a minimum number of the simple arithmetic operations over the carrier period. The evaluation of the hardware resources needed is carried out for the various PLD families produced by Xilinx and accounting for the various parameters of a processed signal. The operational frequency range and the chip power consumption at high clock frequencies are determined. The expression for the calculation of the demodulation error probability is presented. The operability of the demodulator and its high-noise immunity are tested for various signal parameters with the help of statistical simulation methods.