An improved domino logic

Power and area will remain the main constraints in the designing of VLSI circuits. Dynamic CMOS logic circuits are broadly designed for high performance circuits due to their high speed. Conversely, the demerit of dynamic logic style is its high noise sensitivity and during cascading several problems like charge sharing and charge degradation arises. The main cause of this is the sub-threshold leakage current flowing through the pull down network and with continuous technology scaling, this problem is getting more and more severe. Compared to static CMOS circuits which have larger capacitance and offers more delay, Dynamic circuits are used to improve those parameters of design. In this paper we have proposed a new circuit in order to improve the power consumption by applying a multi-threshold technique. Simulations are done in Cadence for 90nm with IBM technology for OR gates with supply voltage of 1v.