Introduction of 95nm SPOCULL technology

SPOCULL is an innovative technology successfully developed by adding a 2
^nd
poly (Poly2, or P2) layer into a mature logic technology as local interconnection (M0), not only the chip area can be reduced significantly but also transistor performance is enhanced. The SPOCULL technology is successfully implemented on 0.13μm CMOS node with logic gate density (~2x than standard 0.13 μm LL technology) and small SRAM cell (size ~0.739μm
²
); this is equivalent to typically 95nm node (thus referred to as 95SPOCULL). Furthermore, the parasitic capacitance and device leakage of transistor is also reduced significantly, e.g. ~30% leakage reduction with same speed of logic standard cells. Also, the P2 layer enables the one-time-programmable (OTP) and multiple-time-programmable (MTP) capability as embedded into the technology platform for MCU. The SPOCULL can also be easily extended to 0.18 μm node similarly.