Variability study of high current junctionless silicon nanowire transistors

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with characteristics required for a specific application, however, poses some challenges. For example, a major challenge is that as the transistors dimensions are reduced, it is difficult to maintain a low off-current (I
_off
) whilst simultaneously maintaining a high on-current (I
_on
). This can be the result of quantum mechanical tunnelling, short channel effects or statistical variability [2]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistor circuits employed globally in microprocessors, sensors and memories.