Hybrid CMOS SET based expandable hardware

For the last five decades, electronic devices matured enough as the transistor size shrunk considerably. There by a new paradigm of ultra small scale device technology appeared and fuelled post CMOS device research. Consequently a classical manifestation of the quantization of electron charge evolved which is referred as Coulomb blocked in single Electronics Technology. This new technology ushered numerous figure of merit in nm scale electronics and soon single electronics was encoded to design logic circuits. But empirical studies revealed the limitations of room temperature based single electronics fabrication. Later on by amalgamating single electronics with conventional CMOS, addressed the limiting factors of single electronics fabrication. The new device principle is attributed as “Hybrid CMOS Single Electronics”. Since the last decade this hybrid topology is considered to design logic circuits similar to CMOS. Here the authors integrate classical CMOS with the uprising single electronics to model an expandable hardware and study its effectiveness to meet the current needs.